Analog-to-Digital Converter (ADC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
28-31
Freescale Semiconductor
Table 28-21. ADC Scan Modes
Scan Mode
Description
Once sequential
Upon START or an enabled sync signal, samples are taken one at a time starting
with SAMPLE0 until a first disabled sample is encountered. If no disabled sample
is encountered in the ADSDIS register, conversion concludes after SAMPLE7. If
the scan is initiated by a sync signal, only one scan is completed until the
converter is rearmed by writing to the CTRL1 register.
Once parallel
Upon START or an armed and enabled sync signal, converter A captures
samples 0-3 and converter B captures samples 4-7. By default
(CTRL2[SIMULT]=1), samples are taken simultaneously (synchronously), and
scanning stops when either converter encounters a disabled sample or both
converters complete all four samples. When SIMULT equals 0, samples are
taken asynchronously, and scanning stops when each converter encounters a
disabled sample in its part of the SDIS register or completes all 4 samples. If the
scan is initiated by a sync signal, only one scan is completed until the converter
is re-armed by writing to the CTRL1 register. (When SIMULT equals 0, the B
converter must be re-armed separately by writing to the CTRL2 register.)
Loop sequential
Upon an initial start or enabled sync pulse, up to 8 samples are taken one at a
time until a disabled sample is encountered. The process repeats until the
STOP0 bit is set. While a loop mode is running, any additional start commands
or sync pulses are ignored. If auto standby (POWER[ASB]=1) or auto
power-down (POWER[APD]=1) is the selected power mode control, the
power-up delay defined by PUDELAY is applied only on the first conversion.
Loop parallel
Upon an initial start or enabled sync pulse, converter A captures Samples 0-3,
and converter B captures Samples 4-7. Each time a converter completes its
current scan, it immediately restarts its scan sequence. This continues until a
STOPn bit is asserted. While a loop is running, any additional start commands
or sync pulses are ignored. By default (CTRL2[SIMULT]=1), samples are taken
simultaneously (synchronously), and scanning stops when either converter
encounters a disabled sample or both converters complete all four samples.
When SIMULT equals 0, samples are taken asynchronously, and scanning stops
when each converter encounters a disabled sample in its part of the SDIS
register or completes all 4 samples. If auto standby or auto power-down is the
selected power mode control, the power-up delay defined by PUDELAY is
applied only on the first conversion.
Triggered sequential
Upon START or an enabled sync signal, samples are taken one at a time starting
with SAMPLE0 until a first disabled sample is encountered. If no disabled sample
is encountered, conversion concludes after SAMPLE7. If external sync is
enabled, new scans are started for each sync pulse that is non-overlapping with
a current scan in progress.
Triggered parallel (default)
Upon START or an enabled sync signal, converter A converts Samples 0-3, and
converter B converts Samples 4-7 in parallel. By default (CTRL2[SIMULT]=1),
samples are taken simultaneously (synchronously), and scanning stops when
either converter encounters a disabled sample or both converters complete all
four samples. When CTRL2[SIMULT] equals 0, samples are taken
asynchronously, and scanning stops when each converter encounters a disabled
sample in its part of the ADSDIS register or completes all 4 samples. If external
sync is enabled (SYNC0=1), new scans are started for each sync pulse as long
as the ADC has completed the previous scan (STAT[CIPn]=0).
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
