Analog-to-Digital Converter (ADC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
28-34
When starting up in normal mode, first set PUDELAY to the large power-up value. Next, clear the PD0
and or PD1 bits to power-up the required converters. Poll the status bits (PSTS
n
in the POWER register)
until all required converters are powered up. Following polling, start scan operations. The value in
PUDELAY provides a power-up delay before scans begin. Because normal mode does not use PUDELAY
at start of scans, no further delays are imposed.
When starting up using auto standby mode, first use the normal mode startup procedure. Before starting
scan operations, set PUDELAY to the smaller value, then set ASB in the POWER register. Auto standby
mode automatically reduces current levels until active and then impose a PUDELAY wait to allow current
levels to rise from standby to normal levels.
When starting up using auto power-down mode, first use the normal mode startup procedure. Before
starting scan operations, set PUDELAY to the large power-up value. Next, set APD in the POWER
register. Finally, clear the PD0 and or PD1 bits for the required converters. Converters remain powered off
until scanning goes active, at which time the large PUDELAY executes as the ADC goes from powered
down to fully powered at the start of the scan.
In auto power-down mode, when the ADC goes from idle to active, a converter is only powered up if it is
required for the scan, as determined by the ADLST1, ADLST2, and SDIS registers.
It is recommended to power-off both converters (PD0=PD1=1 in the POWER register) when
re-configuring clocking or power controls to avoid generating bad samples and ensure proper delays are
applied when powering up or starting scans.
Attempts to start a scan during the PUDELAY time-out are ignored until the appropriate PSTS
n
bits are
cleared in the POWER register.
Any attempt to use a converter when powered down or with the voltage reference disabled results in
invalid results. It is possible to read ADC result registers after converter power down to see results
calculated before power-down. However, a new scan sequence must be started with a SYNC
n
pulse or a
write to the START
n
bit before new results are available.
28.5.8.3
ADC STOP Mode of Operation
Any conversion sequence in progress can be stopped by setting the relevant STOP
n
bit. Any further sync
pulses or writes to the START
n
bit are ignored until the STOP
n
bit is cleared. In this stop mode, the results
registers can be modified by writes from the processor. Any write to ADRSLT
n
in the ADC stop mode is
treated as if the analog core supplied the data, so limit checking, zero crossing, and associated interrupts
can occur if enabled.
28.5.9
ADC Clock
28.5.9.1
General
The ADC has two external clock inputs used to drive two clock domains within the ADC module.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
