ColdFire Core
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
3-11
of the operand address (base register from the RGF and displacement) are selected (DS). Second, the
operand effective address is generated using the ALU execute engine (AG). Third, the memory read
operand is fetched from the core bus, while any required register operand is simultaneously fetched (OC)
from the RGF. Finally, in the fourth cycle, the instruction is executed (EX). The heavily-used 32-bit load
instruction (
move.l <mem>y,Rx
) is optimized to support a two-cycle execution time. The following example
shows an effective address of the form <ea>y = (d16,Ay), i.e., a 16-bit signed displacement
added to a base register Ay.
Figure 3-12. V2 OEP Embedded-Load Part 1
Operand Execution Pipeline
DS
OC
AG
EX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write
RGF
Data
Ay
d16
<ea>y
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Trade
Commission,
BGA-packaged
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
