FlexCAN
30-13
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
•
If FlexCAN is in bus off state, then TXECTR is cascaded together with another internal counter to
count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset
to zero and counts in a manner where the internal counter counts 11 such bits and then wraps
around while incrementing the TXECTR. When TXECTR reaches the value of 128, the
ERRSTAT[FLTCONF] field is updated to be error-active, and both error counters are reset to zero.
At any instance of a dominant bit following a stream of less than 11 consecutive recessive bits, the
internal counter resets itself to zero without affecting the TXECTR value.
•
If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ERRSTAT[ACKERR]
bit). After the transition to error-passive state, the TXECTR does not increment anymore by
acknowledge errors. Therefore, the device never goes to the bus off state.
•
If the RXECTR increases to a value greater than 127, it is not incremented further, even if more
errors are detected while being a receiver. At the next successful message reception, the counter is
set to a value between 119 and 127 to resume to error-active state.
30.3.6
FlexCAN Error and Status Register (ERRSTAT)
ERRSTAT reflects various error conditions, some general status of the device, and is the source of three
interrupts to the CPU. The reported error conditions (bits 15:10) are those occurred since the last time the
CPU read this register. The read action clears bits 15-10. Bits 9–3 are status bits.
Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt flags that
can be cleared by writing 1 to them. Writing 0 has no effect. Refer to
IPSBAR
Offset:
0x1C_001C (ERRCNT)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RXECTR
TXECTR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 30-8. FlexCAN Error Counter Register (ERRCNT)
Table 30-7. ERRCNT Field Descriptions
Field
Description
31–16
Reserved, must be cleared.
15–8
RXECTR
Receive error counter. Indicates current number of receive errors.
7–0
TXECTR
Transmit error counter. Indicates current number of transmit errors.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
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currently
are
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available
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for
import
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sale
in
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
