FlexCAN
Freescale Semiconductor
30-24
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Even with the coherence mechanism described above, writing to the C/S word of active MBs when not in
freeze mode may produce undesirable results. Examples are:
•
Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no
re-evaluation is done to determine a new match/winner. If an Rx MB with a matching ID is
deactivated during the matching process after it was scanned, then this MB is marked as invalid to
receive the frame, and FlexCAN continues looking for another matching MB within the ones it has
not scanned yet. If it can not find one, the message is lost. Suppose, for example, that two MBs
have a matching ID to a received frame, and the user deactivated the first matching MB after
FlexCAN has scanned the second. The received frame is lost even if the second matching MB was
free to receive.
•
If a Tx MB containing the lowest ID is deactivated after the FlexCAN has scanned it, the FlexCAN
looks for another winner within the MBs that it has not yet scanned. Therefore, it may transmit an
MB that may not have the lowest ID at the time because a lower ID might be present that it had
already scanned before the deactivation.
•
There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end
of move-out). After this point, it is transmitted, but no interrupt is issued and the CODE field is not
updated.
30.3.15.2 Locking and Releasing Message Buffers
Besides MB deactivation, FlexCAN has another data coherence mechanism for the receive process. When
the CPU reads the control and status word of an active not empty Rx MB, FlexCAN assumes that the CPU
wants to read the whole MB in an atomic operation, and thus it sets an internal lock flag for that MB.
The lock is released when the CPU reads the free running timer (global unlock operation), or when it reads
the control and status word of another MB. The MB locking is done to prevent a new frame to be written
into the MB while the CPU is reading it.
NOTE
The locking mechanism only applies to Rx MBs which have a code different
than INACTIVE (0000) or EMPTY1 (0100). Also, Tx MBs can not be
locked.
Suppose, for example, that FlexCAN has already received and stored a message into one of the MBs.
Suppose now that the CPU decides to read that MB at the same time another message with the same ID
is arriving. When the CPU reads the control and status word, the MB is locked. The new message arrives
and the matching algorithm finds out that the matching MB is not free to receive It remains in the SMB
waiting for the MB to be unlocked, and only then, is it written to the MB. If the MB is not unlocked in time
and yet another new message with the same ID arrives, then the new message overwrites the one on the
SMB and there is no indication of lost messages in the code field of the MB or in the error and status
register.
While the message is being moved-in from the SMB to the MB, the BUSY bit on the code field is set. If
the CPU reads the control and status word and finds out that the BUSY bit is set, it should defer accessing
the MB until the BUSY bit is cleared.
If the BUSY bit is set or if the MB is empty, then reading the control and status word does not lock the MB.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
