Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-16
Freescale Semiconductor
31.3.8
Data Breakpoint and Mask Registers (DBR, DBMR)
The data breakpoint register (DBR), specify data patterns used as part of the trigger into debug mode. DBR
bits are masked by setting corresponding DBMR bits, as defined in TDR.
DBR and DBMR are accessible in supervisor mode using the WDEBUG instruction and through the BDM
port using the
WDMREG
command.
The DBR supports aligned and misaligned references.
shows relationships between processor
address, access size, and location within the 32-bit data bus.
DRc[4:0]: 0x0E (DBR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Data
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 31-10. Data Breakpoint Registers (DBR)
Table 31-14. DBR Field Descriptions
Field
Description
31–0
Data
Data Breakpoint Value. Contains the value to be compared with the data value from the processor’s local bus as a
breakpoint trigger.
DRc[4:0]: 0x0F (DBMR)
Access: Supervisor write-only
BDM write-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Mask
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Figure 31-11. Data Breakpoint Mask Registers (DBMR)
Table 31-15. DBMR Field Descriptions
Field
Description
31–0
Mask
Data Breakpoint Mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBMR bit allows the
corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit
causes that bit to be ignored.
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
