Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-24
Freescale Semiconductor
Freescale reserves unassigned command opcodes. All unused command formats within any revision level
perform a
NOP
and return the illegal command response
.
The following sections describe the commands summarized in
NOTE
The BDM status bit (S) is 0 for normally completed commands. S is set for
illegal commands, not-ready responses, and transfers with bus-errors.
Section 31.4.1.2, “BDM Serial Interface
,” describes the receive packet
format.
31.4.1.5.1
Read A/D Register (
RAREG
/
RDREG
)
Read the selected address or data register and return the 32-bit result. A bus error response is returned if
the CPU core is not halted.
Command/Result Formats:
Command Sequence:
Figure 31-18.
RAREG
/
RDREG
Command Sequence
Operand Data:
None
Result Data:
The contents of the selected register are returned as a longword value,
most-significant word first.
31.4.1.5.2
Write A/D Register (
WAREG
/
WDREG
)
The operand longword data is written to the specified address or data register. A write alters all 32 register
bits. A bus error response is returned if the CPU core is not halted.
Command Format:
2
0x4 is a three-bit field.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
0x2
0x1
0x8
A/D
Register
Result
D[31:16]
D[15:0]
Figure 31-17.
RAREG
/
RDREG
Command Format
RAREG/RDREG
???
NEXT CMD
LS RESULT
NEXT CMD
’NOT READY’
XXX
BERR
XXX
MS RESULT
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
