Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
31-33
Command Sequence:
Figure 31-34.
SYNC
_
PC
Command Sequence
Operand Data:
None
Result Data:
Command complete status (0xFFFF) is returned when the register write is
complete.
31.4.1.5.10
Read Control Register (
RCREG
)
Read the selected control register and return the 32-bit result. Accesses to the processor/memory control
registers are always 32 bits wide, regardless of register width. The second and third words of the command
form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified
control register. The 12-bit Rc field is the same the processor’s MOVEC instruction uses.
Command/Result Formats:
Command Sequence:
Figure 31-36.
RCREG
Command Sequence
Operand Data:
The only operand is the 32-bit Rc control register select field.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0
0x0
0x0
0x1
Figure 31-33.
SYNC
_
PC
Command Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
0x2
0x9
0x8
0x0
0x0
0x0
0x0
0x0
0x0
Rc
Result
D[31:16]
D[15:0]
Figure 31-35.
RCREG
Command/Result Formats
SYNC_PC
???
NEXT CMD
CMD COMPLETE
XXX
’NOT READY’
RCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
NEXT CMD
’NOT READY’
READ
CONTROL
REGISTER
XXX
BERR
NEXT CMD
MS RESULT
NEXT CMD
LS RESULT
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
