Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-36
Freescale Semiconductor
Figure 31-38.
WCREG
Command Sequence
Operand Data:
This instruction requires two longword operands. The first selects the register to
the operand data writes to; the second contains the data.
Result Data:
Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
31.4.1.5.14
Read Debug Module Register (
RDMREG
)
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the RDMREG command is CSR (DRc=0x00).
Command/Result Formats:
shows the definition of DRc encoding.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command
0x2
0xD
1
0
DRc
Result
D[31:16]
D[15:0]
Figure 31-39.
RDMREG
Command/Result Formats
Table 31-22. Definition of DRc Encoding—Read
DRc[5:0]
Debug Register Definition
Mnemonic
0x00
Configuration/Status
CSR
XXX
’NOT READY’
WCREG
???
MS ADDR
’NOT READY’
MS ADDR
’NOT READY’
WRITE
CONTROL
REGISTER
NEXT CMD
’CMD COMPLETE’
MS DATA
’NOT READY’
NEXT CMD
’NOT READY’
XXX
BERR
LS DATA
’NOT READY’
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
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available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
