Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-40
Freescale Semiconductor
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
31.4.3
Concurrent BDM and Processor Operation
The debug module supports concurrent operation of the processor and most BDM commands. BDM
commands may be executed while the processor is running, except these following operations that access
processor/memory registers:
•
Read/write address and data registers
•
Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
NOTE
Breakpoint registers must be carefully configured in a development system
if the processor is executing. The debug module contains no hardware
interlocks, so TDR should be disabled while breakpoint registers are loaded,
after which TDR can be written to define the exact trigger. This prevents
spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug’s registers (DSCLK must be inactive).
NOTE
The debug module requires the use of the internal bus to perform BDM
commands. For this processor core, if the processor is executing a tight loop
contained within a single aligned longword, the processor may never grant
the internal bus to the debug module, for example:
align4
label1:
nop
bra.b label1
or
align4
label2:
bra.w label2
The processor grants the internal bus if these loops are forced across two
longwords.
31.4.4
Real-Time Trace Support
Real-time trace, which defines the dynamic execution path and is also known as instruction trace, is a
fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into two 4-bit nibbles:
one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to
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MCF52235CVM60
