Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-42
Freescale Semiconductor
31.4.4.1
Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed
on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data
output.
Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only
those target addresses associated with taken branches that use a variant addressing mode (RTE and RTS
instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and
all exception vectors).
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the ColdFire processor uses the debug pins to output the following sequence
of information on two successive processor clock cycles:
1. Use PST (0x5) to identify that a taken branch is executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the DDATA
pins. Encodings 0x9–0xB identify the number of bytes displayed
.
3. The new target address is optionally available on subsequent cycles using the DDATA port. The
number of bytes of displayed on this port is configurable (2, 3, or 4 bytes, where the DDATA
encoding is 0x9, 0xA, and 0xB, respectively).
Another example of a variant branch instruction would be a JMP (A0) instruction.
shows the
PST and DDATA outputs that indicate a JMP (A0) execution, assuming the CSR was programmed to
display the lower 2 bytes of an address.
0xC
Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
0xD
Emulator mode exception processing.
Displayed during emulation mode (debug interrupt or optionally
trace). Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until
exception processing completes.
0xE
Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP instruction.
The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the
stopped mode is exited.
0xF
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until
the processor is restarted or reset. See
”.
Table 31-24. Processor Status Encoding (continued)
PST[3:0]
Definition
Because
of
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from
the
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International
Trade
Commission,
BGA-packaged
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
