Freescale Semiconductor
32-1
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 32
IEEE 1149.1 Test Access Port (JTAG)
32.1
Introduction
The Joint Test Action Group (JTAG) is a dedicated user-accessible test logic compliant with the
IEEE 1149.1 standard for boundary-scan testability, which helps with system diagnostic and
manufacturing testing.
This architecture provides access to all data and chip control pins from the board-edge connector through
the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.
32.1.1
Block Diagram
shows the block diagram of the JTAG module.
Figure 32-1. JTAG Block Diagram
148-bit Boundary Scan Register
TDO/DSO
BKPT
4-bit TAP Instruction Register
3
0
1-bit Bypass Register
32-bit IDCODE Register
TRST/DSCLK
TCLK
TMS/BKPT
0
31
0
TAP Controller
TDI/DSI
1
0
JTAG Module
to Debug Module
4-bit TAP Instruction Decoder
1
0
Disable DSCLK
Force BKPT = 1
DSI = 0
JTAG_EN
DSO
DSI
DSCLK
147
7-bit JTAG_CFM_CLKDIV Register
0
6
3-bit TEST_CTRL Register
0
2
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
