MCF5282 User’s Manual Errata, Rev. 15
Revision History
Freescale Semiconductor
16
5
Revision History
provides a revision history for this document.
E6-E11:F5:F7-F10:
F12:G5:G6:G11:
G12:H5:H6:H11:
H12:J5:J6:J11:J12:
K5:K6:K11:K12:L5:
L7-L10:L12:
M6-M11
VDD
—
—
Positive supply
I
—
A1:A16:E5:E12:F6:
F11:G7-G10:H7-H10:
J7-J10:K7-K10:L6:
L11:M5:M12:T16
VSS
—
—
Ground
I
—
NOTES:
1
Pull-ups are not active when GPIO functions are selected for the pins.
2
The primary functionality of a pin is not necessarily its default functionality. Pins that have GPIO functionality will
default to GPIO inputs.
3
Pull-up is active only with the SYNCA function.
4
Pull-up is active only with the SYNCB function.
5
Pull-up is active only with the SDA function.
6
Pull-up is active only with SCL function.
7
Pull-up is active when JTAG_EN is driven high.
Table 5. Revision History Table
Rev. Number
Substantive Changes
Date of Release
0
Initial release.
07/2003
1
Added page erase verify errata for Chapter 6, “ColdFire Flash Module (CFM).”
09/2003
2
• Added errata for UART interrupt status register.
• Added errata for PIT timer timeout equation.
• Added I2CR write errata.
• Added errata for ‘Internal Pull-Up’ column in ‘MCF5282 Signals and Pin
Numbers Sorted by Function’ table.
• Added errata for “SDRAM Read Cycle’ figure.
11/2003
3
• Added errata for Chapter 19. PIT1–PIT4 should be PIT0–PIT3.
01/2004
4
• Added errata for spurious interrupt.
• Added errata for Table 33-8. Single instance of T
A
= T
L
to T
H
was overlooked
in revision 2.0 of the manual. This instance has now been removed.
03/2004
5
• Added errata for Section 25.4.10: change CANICR to ICRn.
• Added errata for BITERR and ACKERR field descriptions.
• Added errata for BOFFINT and ERRINT bit sequence.
• Added errata for BUFnI field description.
03/2004
Table 14-3. MCF5282 Signals and Pin Numbers Sorted by Function (continued)
MAPBGA Pin
Pin Functions
Description
Primary
I/O
Internal
Pull-up
1
Primary
2
Secondary
Tertiary
