MCF5282 User’s Manual Errata, Rev. 15
Errata for Revision 2.0
Freescale Semiconductor
6
3
Errata for Revision 2.0
Chapter 17
The maximum buffer size of the FEC is 2032 bytes. Replace any mention of the max size
being 2047 bytes with 2032 bytes.
Table 17-2/17-5
In PALR/PAUR entry, delete “(only needed for full duplex flow control)”
Figure 17-23/17-39
Change FRSR to read/write instead of read-only.
25.4.10/25-16
Change CANICR to ICRn.
Table 25-17/25-29
Add the following information to BITERR and ACKERR descriptions: “To clear this bit, first
read it as a one, then write it as a one. Writing zero has no effect.”
Table 25-17/25-30
Change bit ordering: ERRINT should be bit 2 and BOFFINT should be bit 1.
Table 25-19/25-32
Change BUFnI field description from “To clear an interrupt flag, first read the flag as a one,
then write it as a zero” to “To clear an interrupt flag, first read the flag as a one, then write
it as a one.”
Chapter 33
It is crucial during power-up that VDD never exceeds VDDH by more that ~0.3V. There are
diode devices between the two voltage domains, and violating this rule can lead to a
latch-up condition.
Table 33-8/33-7
In the PLL Electrical Specifications table, only specs for the 80MHz MCF5282 device were
listed. Insert specs for the 66MHz device in the first 2 rows and also declare symbol
f
sys(max)
, as shown below:
Table 3. MCF5282UM Rev 2.0 Errata
Location
Description
Table 33-8/33-9
Reference to ‘TA = TL to TH’ was not deleted. Delete.
Table 2. MCF5282UM Rev 2.1 & 2.2 Errata (continued)
Location
Description
Characteristic
Symbol
Min
Max
Unit
66MHz
80MHz
PLL Reference Frequency Range
Crystal reference
External reference
1:1 Mode
f
ref_crystal
f
ref_ext
f
ref_1:1
2
2
33.33
8.33
8.33
66.66
10.0
10.0
80
MHz
System Frequency
1
External Clock Mode
On-Chip PLL Frequency
f
sys
0
f
ref
/ 32
f
sys(max)
66.66
66.66
f
sys(max)
80
80
MHz
