Errata for Revision 2.1 & 2.2
MCF5282 User’s Manual Errata, Rev. 15
Freescale Semiconductor
5
2
Errata for Revision 2.1 & 2.2
Table 33-8/Page 33-7
Change EXTAL Input High Voltage (V
IHEXT
) Crystal Mode minimum spec from “V
DD
- 1.0”
to “V
XTAL
+ 0.4”.
Change EXTAL Input Low Voltage (V
ILEXT
) Crystal Mode maximum spec from “1.0” to
“V
XTAL
- 0.4”.
Section 33.13.1/Page 33-21 Remove second sentence:
“There is no minimum frequency requirement.”
Section 33.13.2/Page 33-22 Remove second sentence:
“There is no minimum frequency requirement.”
Remove second paragraph as this feature is not supported on this device:
“The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to
transition from either the rising or falling edge of ETXCLK, and the timing is the
same in either case. This options allows the use of non-compliant MII PHYs. Refer
to the Ethernet chapter for details of this option and how to enable it.”
Table A-3/Page A-4
The CSMR1 and CSCR1 register addresses are incorrect. They should be
0x090 and 0x096 respectively
Table 2. MCF5282UM Rev 2.1 & 2.2 Errata
Location
Description
Figure 4-2/4-6
Changed bit 23 from DIDI to DISI
Table 4-6/4-9
Under ‘Configuration’ for ‘Instruction Cache’ the ‘Operation’ entry changed to “Invalidate
2 KByte data cache”
Table 4-6/4-9
Under ‘Configuration’ for ‘Data Cache’ the ‘Operation’ entry changed to “Invalidate 2 KByte
instruction cache”
Figure 6-3/6-6
Changed bit 8 to write-only instead of read/write
Table 6-10/6-15
Removed “selected by BKSL[1:0]” as these are internal signal names not necessary for
end-user.
Table 9-4/9-7
In the table for MFD bit definition, footnote (1) equation should read:
Where f
sys(max)
is the maximum system frequency for the particular MCF5282 device
(66MHz or 80MHz)
10.3.2/10-8
Add the following note: ‘If an interrupt source is being masked in the interrupt controller
mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the
status register (SR[I]) is set to a value lower than the interrupt’s level, a spurious interrupt
may occur. This is because by the time the status register acknowledges this interrupt,
the interrupt has been masked. A spurious interrupt is generated because the CPU
cannot determine the interrupt source. To avoid this situation for interrupts sources with
levels 1-6, first write a higher level interrupt mask to the status register, before setting the
mask in the IMR or the module’s interrupt mask register. After the mask is set, return the
interrupt mask in the status register to its previous value. Since level seven interrupts
cannot be disabled in the status register prior to masking, use of the IMR or module
interrupt mask registers to disable level seven interrupts is not recommended.’
Table 1. MCF5282UM Rev 2.3 Errata (continued)
Location
Description
f
sys
f
ref
2 MFD
2
+
(
)
×
2
RFD
----------------------------------------------
f
ref
2 MFD
2
+
(
)
×
f
sys max
(
)
f
sys
f
sys max
(
)
≤
;
≤
;
=
