Document Number: MMA7455L
Rev 10, 12/2009
Freescale Semiconductor
Technical Data
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
±2g/±4g/±8g Three Axis Low-g
Digital Output Accelerometer
The MMA7455L is a Digital Output (I
2
C/SPI), low power, low profile
capacitive micromachined accelerometer featuring signal conditioning, a low
pass filter, temperature compensation, self-test, configurable to detect 0g
through interrupt pins (INT1 or INT2), and pulse detect for quick motion
detection. 0g offset and sensitivity are factory set and require no external
devices. The 0g offset can be customer calibrated using assigned 0g registers
and g-Select which allows for command selection for 3 acceleration ranges
(2g/4g/8g). The MMA7455L includes a Standby Mode that makes it ideal for
handheld battery powered electronics.
Features
•
Digital Output (I
2
C/SPI)
•
3mm x 5mm x 1mm LGA-14 Package
•
Self-Test for Z-Axis
•
Low Voltage Operation: 2.4 V – 3.6 V
•
User Assigned Registers for Offset Calibration
•
Programmable Threshold Interrupt Output
•
Level Detection for Motion Recognition (Shock, Vibration, Freefall)
•
Pulse Detection for Single or Double Pulse Recognition
•
Sensitivity (64 LSB/g @ 2g and @ 8g in 10-Bit Mode)
•
Selectable Sensitivity (±2g, ±4g, ±8g) for 8-bit Mode
•
Robust Design, High Shocks Survivability (5,000g)
•
RoHS Compliant
•
Environmentally Preferred Product
•
Low Cost
Typical Applications
•
Cell Phone/PMP/PDA: Image Stability, Text Scroll, Motion Dialing,
Tap to Mute
•
HDD: Freefall Detection
•
Laptop PC: Freefall Detection, Anti-Theft
•
Pedometer
•
Motion Sensing, Event Recorder
ORDERING INFORMATION
Part Number
Temperature Range
Package
Shipping
MMA7455LT
–40 to +85°C
LGA-14
Tray
MMA7455LR1
–40 to +85°C
LGA-14
7” Tape & Reel
MMA7455LR2
–40 to +85°C
LGA-14
13” Tape & Reel
MMA7455L
MMA7455L: XYZ-AXIS
ACCELEROMETER
±2g/±4g/±8g
14 LEAD
LGA
CASE 1977-01
Bottom View
Figure 1. Pin Connections
Top View
8
9
13
12
10
11
14
1
65
4
3
2
7
AVDD
GND
DVDD_IO
SCL/SPC
CS
INT1/DRDY
INT2
N/C
SDO
SDA/SDI/SDO
N/C
IADDR0
N/C
GND
