Sensors
Freescale Semiconductor
15
MMA7455L
ASSIGNING, CLEARING & DETECTING INTERRUPTS
Assigning the interrupt pins is done in Register $18. There are 3 combinations for the interrupt pins to be assigned which are
outlined below in the table for INTREG[1:0].
Table 7. Configuring the Interrupt settings using Register $18 with INTREG[1:0] bits
00: INT1 Register is detecting Level while INT2 is detecting Pulse.
01: INT1 Register is detecting Pulse while INT2 is detecting Level.
10: INT1 Register is detecting a Single Pulse and INT2 is detecting Single Pulse (if 2
nd
Time Window = 0) or if there is a latency
time window and second time window > 0 then INT2 will detect the double pulse only.
INTPIN: INT1 pin is routed to INT1 bit in Detection Source Register ($0A) and INT2 pin is routed to INT2 bit in Detection Source
Register ($0A).
INTPIN: INT2 pin is routed to INT1 bit in Detection Source Register ($0A) and INT1 pin is routed to INT2 bit in Detection Source
Register ($0A).
Note:
When INTREG[1:0] =10 for the condition to detect single pulse on INT1 and either single or double pulse on INT2, INT1
register bit can no longer be cleared by setting CLR_INT1 bit. It is cleared by setting CLR_INT2 bit. In this case, setting CLR_INT2
clears both INT1 and INT2 register bits and resets the detection operation. Follow the example given for clearing the interrupts.
Clearing the Interrupt Pins: Register $17
CLR_INT1
1: Clear “INT1”
0: Do not clear “INT1”
CLR_INT2
1: Clear “INT2”
0: Do not clear “INT2”
After interrupt has triggered due to a detection, the interrupt pin (INT1 or INT2) need to be cleared by writing a logic 1. Then the
interrupt pin should be enabled to trigger the next detection by setting it to a logic 0.
This example is to show how to reset the interrupt flags
void ClearIntLatch(void)
{
IIC_ByteWrite(INTRST, 0x03);
IIC_ByteWrite(INTRST, 0x00);
}
$18 Control 1 Register
D7
D6
D5
D4
D3
D2
D1
D0
Reg $18
DFBW
THOPT
ZDA
YDA
XDA
INTREG[1]
INTREG[0]
INTPIN
Function
0
0
0
0
0
0
0
0
Default
INTREG[1:0]
“INT1” Register Bit
“INT2” Register Bit
00
Level detection
Pulse Detection
01
Pulse Detection
Level Detection
10
Single Pulse detection
Single or Double Pulse Detection
$17: Interrupt Latch Reset (Read/Write)
D7
D6
D5
D4
D3
D2
D1
D0
Reg $17
--
--
--
--
--
--
CLR_INT2
CLR_INT1
Function
0
0
0
0
0
0
0
0
Default
