Revision History
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
A-3
Preliminary
12
Modified EDMA_CR diagram and field descriptions.
Removed all references to groups and group functions.
Modified SSIZE encoding.
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
13
Modified Figure 13-3 and Figure 13-6.
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
Minor editorial changes.
Changed “n-1” to “n” in Figure 13-2 and all italic x to n.
14
Modified sections 14.4.1 and 14.4.2.
15
Replaced Figure 15-1 with Figure 17-1.Modified Figure 15-1 and added footnote to Figure 15-3.
16
Corrected the reset value of MUDCR in Table 16-1.
Modified MUDCR diagram and field descriptions.
Changed MCMTIR to SWTIR in section 16.2.2.3.
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
Changed flag bits in registers to show w1c., where appropriate.
Modified note in section 16.1 and bullet in section 16.1.1.
17
Corrected Figures 17-5, 17-6, 17-7, 17-8, 17-9.
Added note to reserved bit descriptions in Tables 17-7, 17-9.
Corrected MPU base address in Table 17-1.
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
Various editorial changes.
18
Corrected section 18.3.1 and Table 18-1.
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
Changed CP0INE and CP1INE registers and bit description tables from 32-bit to 16-bit.
19
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
Inserted text in first para.
20
Added note explaining bit numbering convention used.
Removed bit numbers in register bit field descriptions. Redrew flowchart diagrams to allow conversion to sans
serif font. Cleaned up fonts in other diagrams.
Removed bit numbers from bit names used in body text and modified surrounding text for clarification.
Removed everything using MSB=0 condition.
Added SYSCLK/1 as default frequency to Table 20-4 and section 20.5.5.
21
Modified section 21.4.2, and modified sections 21.6 and 21.7.
22
Deleted four lines of text in RWSC row in Table 22-11.
Corrected LLOCK bit sin LML register and field descriptions.
Corrected SLLOCK bits in SLL register and field descriptions.
Corrected LSEL bits in LMS register and field descriptions.
Removed superfluous bit numbers in bit field names. Modified text where necessary to clarify.
Added w1c to flag bits in register diagrams, where appropriate.
Add information to Table 22-1.
Table A-1. Changes Between Revisions 0 and 1 (continued)
Chapter
Description
