MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
10-1
Preliminary
Chapter 10
e200z1 Core (Z1)
10.1
Introduction
The e200 processor family is a set of CPU cores that implement low-cost versions of the Power
Architecture Book E architecture. e200 processors are designed for deeply embedded control applications
that require low cost solutions rather than maximum performance.
The e200z1 processors integrate an integer execution unit, branch control unit, instruction fetch and
load/store units, and a multi-ported register file capable of sustaining three read and two write operations
per clock. Most integer instructions execute in a single clock cycle. Branch target prefetching is performed
by the branch unit to allow single-cycle branches in some cases.
The e200z1 core is a single-issue, 32-bit Power Architecture Book E compliant design with 32-bit general
purpose registers (GPRs). Power Architecture Book E floating-point instructions are not supported by
e200 in hardware, but are trapped and may be emulated by software. All arithmetic instructions that
execute in the core operate on data in the general purpose registers (GPRs).
In addition to the base Power Architecture Book E instruction set support, the core also implements the
VLE (variable-length encoding) APU, providing improved code density. The VLE APU is further
documented in “PowerPC VLE APU Definition, Version 1.01”, a separate document.
In the remainder of this document, the e200z1 core is also referred to as the ‘e200z1 core’ or ‘e200 core’.
10.1.1
Features
The following is a list of some of the key features of the e200z1 core:
•
32-bit Power Architecture Book E programmer’s model
•
Single issue, 32-bit CPU
•
Implements the VLE APU for reduced code footprint
•
In-order execution and retirement
•
Precise exception handling
•
Branch processing unit
— Dedicated branch address calculation adder
— Branch acceleration using Branch Target Buffer
•
Supports independent instruction and data accesses to different memory subsystems, such as
SRAM and Flash memory via independent Instruction and Data BIUs.
•
Load/store unit
— 1 cycle load latency
