e200z1 Core (Z1)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
10-5
Preliminary
•
8-entry fully-associative TLB
•
Support for multiple page sizes from 4 Kbyte to 4 Gbyte
•
Entry flush protection
NOTE
The maximum system frequency is only supported if the MMU control and
status register 0 bypass bit (MMUCSR0[Bypass]) is set to 1, so that address
translation is not performed. If the MMUCSR0[Bypass] bit is 0, then the
maximum system frequency will be less than the maximum frequency listed
in the
MPC5510 Microcontroller Family Data Sheet
.
10.3
Core Registers and Programmer’s Model
This section describes the registers implemented in the e200z1 core. It includes an overview of registers
defined by the Power Architecture Book E architecture, highlighting differences in how these registers are
implemented in the e200 core, and provides a detailed description of e200-specific registers. Full
descriptions of the architecture-defined register set are provided in Power Architecture Book E
Specification.
The Power Architecture Book E defines register-to-register operations for all computational instructions.
Source data for these instructions are accessed from the on-chip registers or are provided as immediate
values embedded in the opcode. The three-register instruction format allows specification of a target
register distinct from the two source registers, thus preserving the original data for use by other
instructions. Data is transferred between memory and registers with explicit load and store instructions
only.
show the e200 register set including the registers which are
accessible while in supervisor mode, and the registers which are accessible in user mode. The number to
the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to
access the register (for example, the integer exception register (XER) is SPR 1).
NOTE
e200z1 is a 32-bit implementation of the Power Architecture Book E
specification. In this document, register bits are sometimes numbered from
bit 0 (most significant bit) to 31 (least significant bit), rather than the Book
E numbering scheme of 32:63, thus register bit numbers for some registers
in Book E are 32 higher.
Where appropriate, the Book E defined bit numbers are shown in
parentheses.
