e200z1 Core (Z1)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
10-9
Preliminary
•
USPRG0. The Power Architecture Book E architecture defines User Software-Use Special
Purpose Register USPRG0 which is accessible in a read-write fashion by user-level software.
10.3.1.2
Supervisor-Level Registers
In addition to the registers accessible in user mode, Supervisor-level software has access to additional
control and status registers used for configuration, exception handling, and other operating system
functions. The Power Architecture Book E defines the following supervisor-level registers:
•
Processor Control Registers
— Machine State Register (MSR). The MSR defines the state of the processor. The MSR can be
modified by the Move to Machine State Register
(
mtmsr
), System Call (
sc, se_sc
), and Return
from Exception (
rfi
,
rfci
,
rfdi, se_rfi
,
se_rfci
,
se_rfdi
)
instructions. It can be read by the Move
from Machine State Register (
mfmsr
)
instruction. When an interrupt occurs, the contents of the
MSR are saved to one of the machine state save/restore registers (SRR1, CSRR1, DSRR1).
— Processor version register (PVR). This register is a read-only register that identifies the
processor type and version (model) and the revision level of the processor.
shows
the PVR values and the corresponding processor type and version numbers for the cores used
on the MPC5510 Family.
— Processor Identification Register (PIR). This read-only register is provided to distinguish the
processor from other processors in the system.
•
Storage Control Register
— Process ID Register (PID, also referred to as PID0). This register is provided to indicate the
current process or task identifier. It is used by the MMU as an extension to the effective address,
and by the Nexus3 module for Ownership Trace message generation. Although the Power
Architecture Book E allows for multiple PIDs, e200z1 implements only one.
•
Interrupt Registers
— Data Exception Address Register (DEAR). After most Data Storage Interrupts (DSI), or on an
Alignment Interrupt or Data TLB Miss Interrupt, the DEAR is set to the effective address (EA)
generated by the faulting instruction.
— SPRG0–SPRG7, USPRG0. The SPRG0–SPRG7 and USPRG0 registers are provided for
operating system use. e200 does not allow user mode access to the SPRG3 register (defined as
implementation dependent by Book E).
— Exception Syndrome Register (ESR). The ESR register provides a syndrome to differentiate
between the different kinds of exceptions that can generate the same interrupt.
— Interrupt Vector Prefix Register (IVPR). This register together with hardwired offsets which
replace the IVOR0-15 registers provide the address of the interrupt handler for different classes
of interrupts.
Table 10-1. PVR Values, and Processor Type and Version Numbers
Device
Core
PVR Value
Type
Version
MPC5516
e200Z1
0x8144_0000
0x14
0x4
MPC5516
e200Z0
0x8171_0000
0x17
0x1
