e200z0 Core (Z0)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
11-8
Freescale Semiconductor
Preliminary
Integer exception register (XER). The XER indicates overflow and carries for integer operations.
See “XER Register (XER),” in Chapter 4, “Integer Operations” of
Power Architecture Book E
Specification
for more information.
•
Link register (LR). The LR provides the branch target address for the Branch to Link Register
(
se_blr
,
se_blrl
) instructions, and is used to hold the address of the instruction that follows a branch
and link instruction, typically used for linking to subroutines. See “Link Register (LR)”, in
Chapter 3, “Branch and Condition Register Operations” of
Power Architecture Book E
Specification
.
•
Count register (CTR). The CTR holds a loop count that can be decremented during execution of
appropriately coded branch instructions. The CTR also provides the branch target address for the
Branch to Count Register (
se_bctr
,
se_bctrl
) instructions. See “Count Register (CTR)”, in
Chapter 3, “Branch and Condition Register Operations” of
Power Architecture Book E
Specification
.
11.3.1.2
Supervisor-Level Registers
In addition to the registers accessible in user mode, Supervisor-level software has access to additional
control and status registers used for configuration, exception handling, and other operating system
functions. The Power Architecture Book E defines the following supervisor-level registers:
•
Processor Control Registers
— Machine State Register (MSR). The MSR defines the state of the processor. The MSR can be
modified by the Move to Machine State Register
(
mtmsr
), System Call (
se_sc
), and Return from
Exception (
se_rfi
,
se_rfci
,
se_rfdi
)
instructions. It can be read by the Move from Machine State
Register (
mfmsr
)
instruction. When an interrupt occurs, the contents of the MSR are saved to
one of the machine state save/restore registers (SRR1, CSRR1, DSRR1).
— Processor version register (PVR). This register is a read-only register that identifies the
processor type and version (model) and the revision level of the processor.
the PVR values and the corresponding processor type and version numbers for the cores used
on the MPC5510 Family.
— Processor Identification Register (PIR). This read-only register is provided to distinguish the
processor from other processors in the system.
•
Storage Control Register
— Process ID Register (PID, also referred to as PID0). This register is provided to indicate the
current process or task identifier. It is used by the Nexus2 module for Ownership Trace message
generation. Although the Power Architecture Book E allows for multiple PIDs, e200z0
implements only one.
•
Interrupt Registers
Table 11-1. PVR Values, and Processor Type and Version Numbers
Device
Core
PVR Value
Type
Version
MPC5516
e200Z1
0x8144_0000
0x14
0x4
MPC5516
e200Z0
0x8171_0000
0x17
0x1
