Enhanced Direct Memory Access (eDMA)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
12-16
Freescale Semiconductor
Preliminary
12.3.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the TCD of the
given channel. The data value on a register write causes the DONE bit in the corresponding transfer control
descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a global clear function, forcing all DONE bits
to be cleared.
12.3.2.13 eDMA Interrupt Request Register (EDMA_IRQRL)
The EDMA_IRQRL provides a bit map for the 16 channels signaling the presence of an interrupt request
for each channel. EDMA_IRQRL maps to channels 15–0.
The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, software must clear the appropriate bit, negating the
interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine is used for this
purpose.
Table 12-13. EDMA_SSBR Field Descriptions
Field
Description
bit 0
Reserved.
SSB[0:6]
Set START Bit (channel service request).
0–15 Set the corresponding channel’s TCD START bit
16–63 Reserved
64–127 Set all TCD START bits
Note: Bits 2 and 3(SSBR[1:2]) are not used.
Offset: EDM 0x001F
Access: User write only
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CDSB[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 12-13. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Table 12-14. EDMA_CDSBR Field Descriptions
Field
Description
bit 0
Reserved.
CDSB[0:6]
Clear DONE Status Bit.
0–15 Clear the corresponding channel’s DONE bit
16–63 Reserved
64–127 Clear all TCD DONE bits
Note: Bits 2 and 3(CDSBR[1:2]) are not used.
