Enhanced Direct Memory Access (eDMA)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
12-30
Freescale Semiconductor
Preliminary
primary transfer control parameter shown in
, for the selected channel into its internal address
path module. As the TCD is being read, the first transfer is initiated on the system bus unless a
configuration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR)
to the destination (as defined by the destination address, TCD.DADDR) continue until the specified
number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the DMA engine's
local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory and any
minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing
is executed; for example, interrupts, major loop channel linking, and scatter-gather operations, if enabled.
shows how each DMA request initiates one minor loop transfer (iteration) without CPU
intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA
preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration
count (biter).
Table 12-20. TCD Primary Control and Status Fields
TCD Field
Name
Description
START
Control bit to start channel when using a software initiated DMA
service (Automatically cleared by hardware)
ACTIVE
Status bit indicating the channel is currently in execution
DONE
Status bit indicating major loop completion (cleared by software
when using a software initiated DMA service)
D_REQ
Control bit to disable DMA request at end of major loop
completion when using a hardware-initiated DMA service
BWC
Control bits for throttling bandwidth control of a channel
E_SG
Control bit to enable scatter-gather feature
INT_HALF
Control bit to enable interrupt when major loop is half complete
INT_MAJ
Control bit to enable interrupt when major loop completes
