Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
16-9
Preliminary
16.2.2.5.2
ECC Status Register (ESR)
The ECC status register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ESR signals the last properly-enabled memory event to be detected. An
ECC interrupt request is asserted if any flag bit is asserted and its corresponding enable bit is asserted.
The MCM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the
association between the ESR and the corresponding address and attribute registers, which are loaded on
each occurrence of an properly-enabled ECC event. If there is a pending ECC interrupt and another
properly-enabled ECC event occurs, the MCM hardware automatically handles the ESR reporting,
clearing the previous data and loading the new state and thus guaranteeing that only a single flag is
asserted.
To maintain the coherent software view of the reported event, the following sequence in the MCM error
interrupt service routine is suggested:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ESR and verify the current contents matches the original contents. If the two values
are different, repeat from step one.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
for the ECC status register definition.
Offset: MCM_BAS 0x0043
Access: User read/write
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
ERNCR
EFNCR
W
Reset
0
0
0
0
0
0
0
0
Figure 16-5. ECC Configuration (ECR) Register
Table 16-6. ECR Field Descriptions
Field
Description
bits 0–5
Reserved.
ERNCR
Enable RAM Non-Correctable Reporting. The occurrence of a non-correctable multi-bit RAM error generates a
MCM ECC interrupt request as signaled by the assertion of ESR[RNCE]. The faulting address, attributes, and
data are also captured in the REAR, RESR, REMR, REAT, and REDR registers.
0 Reporting of non-correctable RAM errors is disabled.
1 Reporting of non-correctable RAM errors is enabled.
EFNCR
Enable Flash Non-Correctable Reporting. The occurrence of a non-correctable multi-bit flash error generates a
MCM ECC interrupt request as signaled by the assertion of ESR[FNCE]. The faulting address, attributes, and
data are also captured in the FEAR, FEMR, FEAT, and FEDR registers.
0 Reporting of non-correctable flash errors is disabled.
1 Reporting of non-correctable flash errors is enabled.
