Memory Protection Unit (MPU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
17-12
Freescale Semiconductor
Preliminary
17.3.2.5
MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
Section 17.3.2.4.3, “MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2)
that because system software may adjust the access controls within a region descriptor
(MPU_RGD
n
.Word2) only as different tasks execute, an alternate programming view of this 32-bit entity
is desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAAC
n
(alternate access control
n
) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGD
n
.Word2.
Figure 17-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Because the MPU_RGDAAC
n
register is another memory mapping for MPU_RGD
n
.Word2, the field
are identical to those presented in
.
Table 17-8. MPU_RGDn.Word3 Field Descriptions
Field
Description
PID
Process Identifier. This 8-bit field specifies that the optional process identifier is to be included in the determination
of whether the current access hits in the region descriptor. This field is combined with the PIDMASK and included in
the region hit determination if MPU_RGDn.Word2[MxPE] is set.
PIDMASK Process Identifier Mask. This 8-bit field provides a masking capability so that multiple process identifiers can be
included as part of the region hit determination. If a bit in the PIDMASK is set, the corresponding bit of the PID is
ignored in the comparison. This field is combined with the PID and included in the region hit determination if
MPU_RGDn.Word2[MxPE] is set. For more information on the handling of the PID and PIDMASK, see
Section 17.4.1.1, “Access Evaluation—Hit Determination
.”
VLD
Valid. This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit, but a write
to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid
1 Region descriptor is valid
Offset: MP 0x800 + (4*n) (MPU_RGDAACn)
Access: Read/write
0
1
2
3
4
5
6
7
8
9
10 11
12
13 14 15
16 17
18
19 20 21
22 23 24 25 26 27
28 29 30 31
R
M
4
R
E
M
4
W
E
M
3
P
E
M3SM
M3UM
r w
x
M
2
P
E
M2SM
M2UM
r w
x
M
1
P
E
M1SM
M1UM
r w
x
M
0
P
E
M0SM
M0UM
r w
x
W
Reset – – – – – – – – –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– –
–
–
–
–
–
Table 17-9. MPU_RGDAACn Field Descriptions
Field
Description
bits 0–5
Reserved.
Note: These bits must never be set.
M4RE
Bus Master ID 4 Read Enable. If set, this flag allows bus master ID 4 to perform read operations. If cleared, any
attempted read by bus master ID 4 terminates with an access error and the read is not performed.
