Memory Protection Unit (MPU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
17-13
Preliminary
M4WE
Bus Master 4 Write Enable. If set, this flag allows bus master 4 to perform write operations. If cleared, any attempted
write by bus master 4 terminates with an access error and the write is not performed.
M3PE
Bus Master 3 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, the region hit evaluation does not
include the process identifier.
M3SM
Bus Master 3 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master 3 when
operating in supervisor mode. The M3SM field is defined as:
00
r, w, x =
read, write and execute allowed
01
r, –, x =
read and execute allowed, but no write
10
r, w, – =
read and write allowed, but no execute
11 Same access controls as that defined by M3UM for user mode
M3UM
Bus Master 3 User Mode Access Control. This 3-bit field defines the access controls for bus master 3 when operating
in user mode. The M3UM field consists of three independent bits, enabling read, write, and execute permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be
terminated with an access error (if not allowed by any other descriptor) and the access not performed.
M2PE
Bus Master 2 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, the region hit evaluation does not
include the process identifier.
M2SM
Bus Master 2 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master 2 when
operating in supervisor mode. The M2SM field is defined as:
00
r, w, x =
read, write and execute allowed
01
r, –, x =
read and execute allowed, but no write
10
r, w, – =
read and write allowed, but no execute
11 Same access controls as that defined by M2UM for user mode
M2UM
Bus Master 2 User Mode Access Control. This 3-bit field defines the access controls for bus master 2 when operating
in user mode. The M2UM field consists of three independent bits, enabling read, write, and execute permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be
terminated with an access error (if not allowed by any other descriptor) and the access not performed.
M1PE
Bus Master 1 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, the region hit evaluation does not
include the process identifier.
M1SM
Bus Master 1 Supervisor Mode Access Control. This 2-bit field defines the access controls for bus master 1 when
operating in supervisor mode. The M1SM field is defined as:
00
r, w, x =
read, write and execute allowed
01
r, –, x =
read and execute allowed, but no write
10
r, w, – =
read and write allowed, but no execute
11 Same access controls as that defined by M1UM for user mode
M1UM
Bus Master 1 User Mode Access Control. This 3-bit field defines the access controls for bus master 1 when operating
in user mode. The M1UM field consists of three independent bits, enabling read, write, and execute permissions:
{r,w,x}
. If set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be
terminated with an access error (if not allowed by any other descriptor) and the access not performed.
M0PE
Bus Master 0 Process Identifier Enable. If set, this flag specifies that the process identifier and mask (defined in
MPU_RGDn.Word3) are to be included in the region hit evaluation. If cleared, then the region hit evaluation does not
include the process identifier.
Table 17-9. MPU_RGDAACn Field Descriptions (continued)
Field
Description
