Semaphores
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
18-13
Preliminary
else
locked_value = CP1_LOCK;
/* read the current value of the gate and wait until the state == UNLOCK */
do {
current_value = gate[n];
} while (current_value != UNLOCK);
/* the current value of the gate == UNLOCK. attempt to lock the gate for this
processor. spin-wait in this loop until gate ownership is obtained */
do {
gate[n] = locked_value;
/* write gate with processor_ 1 */
current_value = gate[n];
/* read gate to verify ownership was obtained */
} while (current_value != locked_value);
}
•
To unlock (open) a gate
— After completing the protected code segment, the locking processor performs a byte write of
zeroes to gate[i], unlocking (opening) the gate
In this example, a reference to
processor_number()
is used to retrieve this hardware configuration
value. Typically, the logical processor numbers are defined by a hardwired input vector to the individual
cores. The exact method for accessing the logical processor number varies by architecture. For PowerPC
cores, there is a processor ID register (PIR) which is SPR 286 and contains this value. A single instruction
can be used to move the contents of the PIR into a general-purpose register:
mfspr rx,286 where rx is the
destination GPRn. Other architectures may support a specific instruction to move the contents of the
logical processor number into a general-purpose register, e.g.,
rdcpn rx
for a read CPU number
instruction.
If the optional failed lock IRQ notification mechanisms are used, then accesses to the related registers
(SEMA4_CPnINE, SEMA4_ CPnNTF) are required. There is no required negation of the failed lock write
notification interrupt as the request is automatically negated by the semaphores module once the gate has
been successfully locked by the failing processor.
Finally, in the event a system state requires a software-controlled reset of a gate or IRQ notification
register(s), accesses to the secure reset control registers (SEMA4_RSTGT, SEMA4_RSTNTF) are
required. For these situations, it is recommended that the appropriate IRQ notification enable(s)
(SEMA4_CPnINE) bits be disabled before initiating the secure reset 2-write sequence to avoid any race
conditions involving spurious notification interrupt requests.
18.7
DMA Requests
There are no DMA requests associated with the IPS_Semaphore block.
18.8
Interrupt Requests
The semaphore interrupt requests are connected to the interrupt controller as described in
.
