IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
19-4
Freescale Semiconductor
Preliminary
TDO output from the selected TAP controller is sent back to the JTAGC to be output on the pins. The
JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was
entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive.
For more information on the TAP controllers see
Chapter 20, “Nexus Development Interface (NDI)
.”
19.2
External Signal Description
Refer to
Section 2.7, “Detailed External Signal Descriptions
,” for detailed signal
descriptions.
19.3
Memory Map and Registers
This section provides a detailed description of the JTAGC registers accessible through the TAP interface,
including data registers and the instruction register. Individual bit-level descriptions and reset states of
each register are included. These registers are not memory-mapped and can be accessed through the TAP
only.
19.3.1
Instruction Register
The JTAGC uses a 5-bit instruction register as shown in
. The instruction register allows
instructions to be loaded into the module to select the test to be performed or the test data register to be
accessed or both. Instructions are shifted in through TDI while the TAP controller is in the Shift-IR state,
and latched on the falling edge of TCK in the Update-IR state. The latched instruction value can be
changed in the Update-IR and Test-Logic-Reset TAP controller states only. Synchronous entry into the
test-logic-reset state results in the IDCODE instruction being loaded on the falling edge of TCK.
Asynchronous entry into the test-logic-reset state results in asynchronous loading of the IDCODE
instruction. During the capture-IR TAP controller state, the instruction shift register is loaded with the
value 0b10101, making this value the register’s read value when the TAP controller is sequenced into the
Shift-IR state.
19.3.2
Bypass Register
The bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDO
when the BYPASS, CLAMP, HIGHZ, or reserve instructions are active. After entry into the capture-DR
state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the
bypass register is always a logic 0.
0
1
2
3
4
R
1
0
1
0
1
W
Instruction Code
Reset
0
0
0
0
1
Figure 19-3. 5-Bit Instruction Register
