Flash Array and Control
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
22-15
Preliminary
errors take priority over state machine errors. This is especially valuable in the event of a RWW operation,
where the read senses an ECC error and the state machine fails simultaneously. This address is always a
doubleword address that selects 64 bits.
In normal operating mode, the ADR is not writable.
22.4.2.8
Platform Flash Configuration Register for Port n (PFCRPn)
The PFLASH configuration register for port 0 (PFCRP0) is used to specify operation of port p0 of the
PFLASH2P_H7Fb. This register also has two bits (ARB and PRI) to control arbitration between the p0/p1
ports.
The PFLASH configuration register for port 1 (PFCRP1) is used to specify operation of port p1 of the
PFLASH2P_H7Fb
Offset: FLASH_REG 0x0018
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
ADDR[10:15]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
ADDR[16:28]
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-10. Address Register (ADR)
Table 22-10. ADR Field Descriptions
Field
Description
bits 0–9
Reserved.
ADDR
Doubleword address of first failing address in the event of an ECC error or the address of a failure occurring
during state machine operation.
bits 29–31
Reserved.
