Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-34
Freescale Semiconductor
Preliminary
The TX FIFO counter field (TXCTR) in the DSPI status register (DSPI
x
_SR) indicates the number of valid
entries in the TX FIFO. The TXCTR is updated every time the DSPI _PUSHR is written or SPI data is
transferred into the shift register from the TX FIFO. For more information on DSPI
x
_SR, refer to
Section 23.3.2.4, “DSPI Status Register (DSPI_SR)
The TXNXTPTR field indicates which TX FIFO entry will be transmitted during the next transfer. The
TXNXTPTR contains the positive offset from DSPI
x
_TXFR0 in number of 32-bit registers. For example,
TXNXTPTR equal to two means that the DSPI
x
_TXFR2 contains the SPI data and command for the next
transfer. The TXNXTPTR field is incremented every time SPI data is transferred from the TX FIFO to the
shift register.
23.4.3.4.1
Filling the TX FIFO
Host software or the eDMA controller can add (push) entries to the TX FIFO by writing to the
DSPI
x
_PUSHR. When the TX FIFO is not full, the TX FIFO fill flag (TFFF) in the DSPI
x
_SR is set. The
TFFF bit is cleared when the TX FIFO is full and the eDMA controller indicates that a write to
DSPI
x
_PUSHR is complete or alternatively by host software writing a 1 to the TFFF in the DSPI
x
_SR.
The TFFF can generate a DMA request or an interrupt request. See
Section 23.4.11.2, “Transmit FIFO Fill
Interrupt or DMA Request (TFFF)
,” for details.
The DSPI ignores attempts to push data to a full TX FIFO; that is, the state of the TX FIFO is unchanged.
No error condition is indicated.
23.4.3.4.2
Draining the TX FIFO
The TX FIFO entries are removed (drained) by shifting SPI data out through the shift register. Entries are
transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the
TX FIFO. Every time an entry is transferred from the TX FIFO to the shift register, the TX FIFO counter
is decremented by one. At the end of a transfer, the TCF bit in the DSPI
x
_SR is set to indicate the
completion of a transfer. The TX FIFO is flushed by writing a 1 to the CLR_TXF bit in DSPI
x
_MCR.
If an external SPI bus master initiates a transfer with a DSPI slave while the slave’s DSPI TX FIFO is
empty, the transmit FIFO underflow flag (TFUF) in the slave’s DSPI
x
_SR is set. See
“Transmit FIFO Underflow Flag (TFUF)
,”for details.
23.4.3.5
Receive First-In First-Out (RX FIFO) Buffering Mechanism
The RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds four received
SPI data frames. SPI data is added to the RX FIFO at the completion of a transfer when the received data
in the shift register is transferred into the RX FIFO. SPI data is removed (popped) from the RX FIFO by
reading the DSPI
x
_POPR register. RX FIFO entries can only be removed from the RX FIFO by reading
the DSPI
x
_POPR or by flushing the RX FIFO. For more information on the DSPI
x
_POPR, refer to
Section 23.3.2.7, “DSPI POP RX FIFO Register (DSPI_POPR)
.”
The RX FIFO counter field (RXCTR) in the DSPI status register (DSPI
x
_SR) indicates the number of
valid entries in the RX FIFO. The RXCTR is updated every time the DSPI _POPR is read or SPI data is
copied from the shift register to the RX FIFO.
