Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
25-4
Freescale Semiconductor
Preliminary
25.1.3.3
Listen-Only Mode
In this mode, transmission is disabled, all error counters are frozen and the module operates in a CAN error
passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects
a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it
was trying to acknowledge the message.
25.1.3.4
Loop-Back Mode
The module enters this mode when the LPB bit in the control register is asserted. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN
output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting, and
treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception
of its own message. Transmit and receive interrupts are generated.
25.1.3.5
Module-Disabled Mode
This low-power mode is entered when the MDIS bit in the CANx_MCR register is asserted. When
disabled, the clocks to the CAN protocol interface and message buffer management submodules are shut
down. Exit from this mode is done by negating the MDIS bit in the CANx_MCR register.
25.1.3.6
Stop Mode
This low-power mode is entered when stop mode is requested at MCU level. When in stop mode, the
module puts itself in an inactive state and then informs the CPU that the clocks can be shut down globally.
Exit from this mode happens when the stop mode request is removed or when activity is detected on the
CAN bus and the self wake up mechanism is enabled.
25.2
External Signal Description
Please refer to
Chapter 2, “Signal Descriptions
,” for a complete description of the FlexCAN
signals.
25.3
Memory Map and Registers
This section provides a detailed description of all FlexCAN registers.
25.3.1
Module Memory Map
The complete memory map for an individual FlexCAN module is shown in
addresses, all FlexCAN modules have identical memory maps.
The Rx global mask (CANx_RXGMASK), Rx buffer 14 mask (CANx_RX14MASK) and the Rx buffer
15 mask (CANx_RX15MASK) registers are provided for backwards compatibility, and are not used when
the BCC bit in CANx_MCR is asserted.
