Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
25-18
Freescale Semiconductor
Preliminary
25.3.4.3
Free-Running Timer (CANx_TIMER)
This register represents a 16-bit free-running counter that can be read and written by the CPU. The timer
starts from 0x0000 after Reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a
message transmission/reception, it increments by one for each bit that is received or transmitted. When
there is no message on the bus, it counts using the previously programmed baud rate. During Freeze Mode,
the timer is not incremented.
The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. This
captured value is written into the Time Stamp entry in a message buffer after a successful reception or
transmission of a message.
Writing to the timer is an indirect operation. The data is first written to an auxiliary register and then an
internal request/acknowledge procedure across clock domains is executed. All this is transparent to the
user, except for the fact that the data will take some time to be actually written to the register. If desired,
software can poll the register to discover when the data was actually written.
25.3.4.4
Rx Mask Registers
By negating the CANx_MCR[BCC] bit, the CANx_RXGMASK, CANx_RX14MASK, and
CANx_RX15MASK registers are used as acceptance masks for received frame IDs. Three masks are
defined: a global mask, used for Rx buffers 0
–
13 and 16
–
63, and two extra masks dedicated for buffers 14
and 15. The meaning of each mask bit is the following:
•
Mask bit = 0: the corresponding incoming ID bit is “don’t care.”
•
Mask bit = 1: the corresponding ID bit is checked against the incoming ID bit, to see if a match
exists.
Note that these masks are used both for standard and extended ID formats. The value of mask registers
should not be changed while in normal operation. Locked frames which had matched a MB through a mask
may be transferred into the MB (upon release) but may no longer match.
shows some examples
of ID masking for standard and extended message buffers.
Offset: Base + 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
TIMER
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-7. Free-Running Timer (CANx_TIMER)
