Enhanced Modular I/O Subsystem (eMIOS200)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
26-13
Preliminary
IF
Input Filter Bits. The IF bits control the programmable input filter, selecting the minimum input pulse width that
can pass through the filter. For output modes, these bits have no meaning.
FCK
Filter Clock Select Bit. The FCK bit selects the clock source for the programmable input filter.
0 Prescaled clock
1 Main clock
FEN
FLAG Enable Bit. The FEN bit allows the unified channel FLAG bit to generate an interrupt signal or a DMA
request signal (the type of signal to be generated is defined by the DMA bit).
0 Disable (FLAG does not generate an interrupt or DMA request)
1 Enable (FLAG will generate an interrupt or DMA request)
FORCMA
Force Match A Bit. For output modes, the FORCMA bit is equivalent to a successful comparison on
comparator A (except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This
bit is valid for every output operation mode which uses comparator A, otherwise it has no effect.
0 Has no effect
1 Force a match at comparator A
For input modes, the FORCMA bit is not used and writing to it has no effect.
FORCMB
Force Match B Bit. For output modes, the FORCMB bit is equivalent to a successful comparison on
comparator B (except that the FLAG bit is not set). This bit is cleared by reset and is always read as 0. This
bit is valid for every output operation mode which uses comparator B, otherwise it has no effect.
0 Has no effect
1 Force a match at comparator B
For input modes, the FORCMB bit is not used and writing to it has no effect.
Table 26-9. EMIOS_CCR[n] Field Descriptions (continued)
Field
Description
IF
1
1
Filter latency is three clock edges.
Minimum Input Pulse Width
[FLT_CLK Periods]
0000
Bypassed
2
0001
02
0010
04
0100
08
1000
16
All others
Reserved
2
The input signal is synchronized before arriving to the digital filter.
