Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
31-7
Preliminary
0x005C
Reserved
0x0060
eQADC Interrupt and eDMA Control Register 0
(EQADC_IDCR0)
R/W
0x0062
eQADC Interrupt and eDMA Control Register1
(EQADC_IDCR1)
R/W
0x0064
eQADC Interrupt and eDMA Control Register 2
(EQADC_IDCR2)
R/W
0x0066
eQADC Interrupt and eDMA Control Register 3
(EQADC_IDCR3)
R/W
0x0068
eQADC Interrupt and eDMA Control Register 4
(EQADC_IDCR4)
R/W
0x006A
eQADC Interrupt and eDMA Control Register 5
(EQADC_IDCR5)
R/W
0x006C
Reserved
0x0070
eQADC FIFO and Interrupt Status Register 0
(EQADC_FISR0)
R/W
0x0074
eQADC FIFO and Interrupt Status Register 1
(EQADC_FISR1)
R/W
0x0078
eQADC FIFO and Interrupt Status Register 2
(EQADC_FISR2)
R/W
0x007C
eQADC FIFO and Interrupt Status Register 3
(EQADC_FISR3)
R/W
0x0080
eQADC FIFO and Interrupt Status Register 4
(EQADC_FISR4)
R/W
0x0084
eQADC FIFO and Interrupt Status Register 5
(EQADC_FISR5)
R/W
0x0088
Reserved
0x008C
Reserved
Table 31-1. eQADC Memory Map (continued)
Offset from
EQADC_BASE
(0xFFF8_0000)
Register
Access
Reset Value
Section/Page
