Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
31-46
Freescale Semiconductor
Preliminary
The eQADC trigger numbers specified by SIU_ETISR[TSEL(0-5)] correspond to CFIFO numbers 0-5. To
calculate the CFIFO number that each trigger is connected to, divide the eDMA channel number by 2.
31.4.3.4
External Trigger Event Detection
The digital filter length field in
Section 31.3.3.3, “eQADC External Trigger Digital Filter Register
,” specifies the minimum number of system clocks that the external trigger signals 0
and 1 must be held at a logic level to be recognized as valid. All ETRIG signals are filtered. A counter for
each queue trigger is implemented to detect a transition between logic levels. The counter counts at the
system clock rate. The corresponding counter is cleared and restarted each time the signal transitions
between logic levels. When the corresponding counter matches the value specified by the digital filter
length field in
Section 31.3.3.3, “eQADC External Trigger Digital Filter Register (EQADC_ETDFR)
,” the
eQADC considers the ETRIG logic level to be valid and passes that new logic level to the rest of the
eQADC.
The filter is only for filtering the ETRIG signal. Logic after the filter checks for transitions between filtered
values, such as for detecting the transition from a filtered logic level zero to a filtered logic level one in
rising edge external trigger mode. The eQADC can detect rising edge, falling edge, or level gated external
triggers. The digital filter will always be active independently of the status of the MODE
n
field in
Section 31.3.3.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn)
,” but the edge, level
detection logic is only active when MODE
n
is set to a value different from disabled, and in case MODE
n
is set to single scan mode, when the SSS bit is asserted. Note that the time necessary for a external trigger
event to result into a CFIFO status change is not solely determined by the DFL field in the
“eQADC External Trigger Digital Filter Register (EQADC_ETDFR)
.” After being synchronized to the
system clock and filtered, a trigger event is checked against the CFIFO trigger mode. Only then, after a
valid trigger event is detected, the eQADC accordingly changes the CFIFO status. Refer to
for an example.
Figure 31-30. ETRIG Event Propagation Example
31.4.3.5
CFIFO Scan Trigger Modes
The eQADC supports two different scan modes, single-scan and continuous-scan. Refer to
for
a summary of these two scan modes. When a CFIFO is triggered, the eQADC scan mode determines
whether the eQADC will stop command transfers from a CFIFO, and wait for software intervention to
rearm the CFIFO to detect new trigger events, upon detection of an asserted EOQ bit in the last transfer.
Refer to
Section 31.4.1.1, “Message Format in eQADC
,” for details about command formats.
External Trigger Signal
Signal State at Input Pin
Idle
Waiting for Trigger
Triggered
Disabled
Continuous-Scan High Level Gated External Trigger
System Clock
CFIFO Status
MODE
n
Filtered External
Trigger Signal
Trigger Synchronization & Filtering Delay
Trigger Detection Delay
