Frequency Modulated Phase Locked Loop (FMPLL)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
4-15
Preliminary
4.4.3.3.5
Programming System Clock Frequency
In normal PLL clock mode, the default system frequency is determined by the default EPREDIV, EMFD,
and ERFD values.
When programming the PLL, do not to violate the maximum system clock frequency or max/min VCO
frequency specifications. Based on the desired system clock frequency, EPREDIV, EMFD, and ERFD
must be calculated for the given crystal or external reference frequency. See
MPC5510 Microcontroller
Family Data Sheet
for the max/min VCO frequency range and the maximum allowable system frequency.
Frequency modulation should be disabled prior to changing the EPREDIV, EMFD, or RATE bit fields.
After enabling frequency modulation a new calibration sequence is performed. A change to EPREDIV,
EMFD, DEPTH, or RATE while modulation is enabled will invalidate the previous calibration results.
Use these directions to accommodate the frequency overshoot that occurs when the EPREDIV or EMFD
bits are changed. If frequency modulation is going to be enabled the maximum allowable frequency must
be reduced by the programmed
Δ
F
m
.
1. Determine the appropriate value for the EPREDIV, EMFD, and ERFD fields in the synthesizer
control register(s), remember to include the
Δ
F
m
if frequency modulation is to be enabled. The
amount of jitter in the system clocks can be minimized by selecting the maximum EMFD factor
that can be paired with an ERFD factor to provide the desired frequency. The maximum EMFD
value that can be used is determined by the VCO and EMFD range.
2. Write a value of ERFD = ERFD (from step 1) + 1 to the ERFD field of the ESYNCR2. Not
increasing the ERFD when changing the EPREDIV or EMFD could subject the device to clock
frequencies beyond the range specified for the device due to the PLL’s unlocked state.
3. If frequency modulation is currently enabled, disable it by writing 00 to the EDEPTH field of the
ESYNCR2.
4. If programming the EPREDIV and/or EMFD, write the value(s) determined in step 1 to the
appropriate field(s) in the ESYNCR1.
5. Monitor the synthesizer lock bit (LOCK) in the synthesizer status register (SYNSR). When the
PLL achieves lock, write the ERFD value determined in step 1 to the ERFD field of the ESYNCR2.
This changes the system clocks frequency to the desired frequency. If frequency modulation is
desired, leave ERFD programmed to ERFD + 1 until after completing the steps in
Section 4.4.3.4.2, “Programming System Clock Frequency With Frequency Modulation
.
”
6. If frequency modulation was enabled initially, it can be re-enabled following the steps listed in
Section 4.4.3.4.2, “Programming System Clock Frequency With Frequency Modulation
.
”
4.4.3.4
PLL Normal Mode With Frequency Modulation
In normal PLL clock mode, frequency modulation is not enabled in the default synthesis mode. When
frequency modulation is enabled two parameters must be set to generate the desired level of modulation.
The parameters to be programmed are the RATE and DEPTH bit fields of the ESYNCR2 register. The
RATE bit controls the frequency of modulation, F
mod
. The DEPTH bits work to control the modulation
depth, F
m
. The available modulation rates and depths are given in
, respectively.
The modulation waveform is always a triangle wave and its shape is not programmable. An example of
one period of the modulation waveform is shown in
