Media Local Bus (MLB)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
33-11
Preliminary
33.3.1.6
TX Control Channel Address Register (MLB_TXCCHAR)
The MLB_TXCCHAR contains the TX Control Channel Address for this device.
Offset M0x0010
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
RXA
CHA_
A
CEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
RXACHA
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 33-6. MLB RX Async Channel Address Register (MLB_RXACHAR)
Table 33-7. MLB RX Async Channel Address Register (MLB_RXACHAR) Field Descriptions
Field
Description
RXACHA_ACEN
RX Async Channel Address Comparison Enable. When enabled a received Channel Address is
compared against the RX Async Channel Address configured in this register. RXACHA_ACEN should
only be updated when MDIS is set.
0 RX Async Channel Address comparison disabled (default out of reset)
1 RX Async Channel Address comparison enabled
bits 1–25
Reserved.
RXACHA
RX Async Channel Address. If RXACHA_ACEN=1, this address will be compared against the logical
address that was driven on the bus by the MLB controller (INIC). If the received channel address matches
the programmed value in the MLB_RXACHAR register the appropriate output buffer enables are driven
(
Section 33.4.2.1.4, “MLBSIG_BUFEN and MLBDAT_BUFEN
”).
Although Channel Addresses are defined to be sixteen bits wide, bits 15 through 9 and the LSB are
always zero. The odd addresses are reserved and Channel Address 0x0000 is the bus idle state. Only
the 31 even addresses between 0x0002 and 0x003E are allowed; therefore, only five bits per Channel
Address are required to be configured. RXACHA should only be updated when MDIS is set.
An address match occurs when RXACHA_ACEN is set and the received 16 bit Channel Address equals
16b0000_0000_00_{RXACHA}_0.
bit 31
Reserved.