Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
5-11
Preliminary
NOTE
The user may attempt to set both the CRP_Z1VEC[Z1RST] and
CRP_Z0VEC[Z0RST] bits to 1, but if one of these bits is already set to a
value of 1, the write to the other bit will be blocked.
If both cores are running, either core can stop the other core by writing to
the other core’s reset bit.
5.2.2.7
Z0 Reset Vector Register (CRP_Z0VEC)
The CRP_Z0VEC register contains:
•
Recovery vector for the Z0 core
•
Reset for the Z0 core
Offset: CR 0x0050
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Z1VEC
Z1
R
S
T
V
L
E
W
Reset 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Figure 5-7. Z1 Reset Vector Register (CRP_Z1VEC)
Table 5-8. CRP_Z1VEC Field Descriptions
Field
Description
Z1VEC
Z1 Recovery Vector. The Z1VEC value determines the initial program counter for the Z1 upon exiting reset.
On POR, the value contained in the register defaults to 0xFFFF_FFFD, so that the Z1 fetches VLE code from
the BAM starting at address 0xFFFF_FFFC. The user may change this value to point to a different memory
location for system reinitialization upon low-power sleep mode exit.
30
Z1RST
Controls the assertion of RESET to the Z1 core. Writes to this bit cause the Z1 to immediately enter/exit reset.
Reads of this bit indicate if the core is being held in reset.
0 Z1 not in reset
1 Z1 in reset
31
VLE
VLE Select. The VLE bit selects whether the Z1 recovers into VLE or Book E mode.
0 Book E
1 VLE
Offset: CR 0x0054
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Z0VEC
Z0
R
S
T
0
W
Reset 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Figure 5-8. Z0 Reset Vector Register (CRP_Z0VEC)
