Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
5-12
Freescale Semiconductor
Preliminary
NOTE
The user may attempt to set the CRP_Z1VEC[Z1RST] and
CRP_Z0VEC[Z0RST] bits to 1, but if one of these bits is already set to a
value of 1, the write to the other bit will be blocked.
If both cores are running, either core can stop the other core by writing to
the other core’s reset bit.
5.2.2.8
Reset Recovery Pointer Register (CRP_RECPTR)
The CRP_RECPTR register contains:
•
Recovery pointer
•
Fast recovery enable
Table 5-9. CRP_Z0VEC Field Descriptions
Field
Description
Z0VEC
Z0 Recovery Vector. The Z0VEC value determines the initial program counter for the Z0 upon exiting reset.
On POR, the value contained in the register defaults to 0xFFFF_FFFE, and the Z0 is held in reset. Change
this value to point to a different memory location for Z0 specific initialization upon negation of the Z0RST bit,
or to a location for the Z0 to start running code when exiting Low Power modes (if it was not in RESET before
entering the low power mode).
Z0RST
Controls the assertion of RESET to the Z0 core. Writes to this bit cause the Z0 to immediately enter/exit reset.
Reads of this bit indicate if the core is being held in reset.
0 Z0 not in reset.
1 Z0 in reset.
bit 31
Reserved.
Offset: CR 0x0058
Access: User read only
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30
31
R
RECPTR
FASTREC
0
W
Reset 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
Figure 5-9. Reset Recovery Pointer (CRP_RECPTR)
Table 5-10. CRP_RECPTR Field Descriptions
Field
Description
RECPTR
Recovery Pointer. The RECPTR value is a generic 30 bit register available to the user application which
retains a value during all low-power modes. This register may be used by the user software to indicate where
in RAM a recovery routine exists. On reset, this register defaults to 0xFFFF_FFFC so that it points to the same
location as the Z1VEC and Z0VEC registers.
