Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
5-26
Freescale Semiconductor
Preliminary
Figure 5-17. External Pin Wakeup Logic
5.3.4.1
Low Power Mode Debug Support
The CRP supports debug after exit from both SLEEP and STOP modes for both Nexus and JTAG debug
tools. This function is enabled by setting the NPC PCR LP_DBG bit prior to entry into SLEEP/STOP
modes.
On entry into STOP mode, if the NPC PCR LP_DBG bit is set, the CRP sets the NPC PCR STOP_SYNC
bit to inform the debug tool that STOP mode is being entered. The CRP waits for this bit to be cleared
before proceeding into STOP mode. During STOP mode, the entire SOC remains powered. The pad
keepers are released immediately on wakeup from STOP mode. Any debug functionality that was enabled
prior to STOP mode will be enabled after waking up from STOP mode. On exit from STOP mode, after
the system clock is started, the CRP asserts the TDO pin in order to inform the debug tool of STOP mode
exit. The TDO pin remains asserted until the debug tool sets the STOP_SYNC bit in the NPC PCR register.
In order for the debug tool not to miss instruction execution, the CRP does not assert the wakeup interrupt
to the Z0 and Z1 cores until after the debug tool has acknowledged the TDO assertion.
0
1
32 kHz IRC
16 MHz IRC
External Pin Group n
3
CRP_WKPINSEL
CRP_WKSE
Edge
detect
logic
2
CRP_WKSE
CRP_PSCR
8 to 1
MUX
To Wakeup Logic
CRP_PSCR
[PWKSRCFn]
NOTE: This logic is repeated for each of the eight pin wakeup groups
[WKPSELn]
[WKCLKSEL]
[WKPDETn]
[PWKSRIEn]
To
interrupt
controller
