System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
6-34
Freescale Semiconductor
Preliminary
6.3.2.19
Chip Configuration Register (SIU_CCR)
6.3.2.20
External Clock Control Register (SIU_ECCR)
The SIU_ECCR controls the timing relationship between the system clock and the external clocks,
CLKOUT. All bits and fields in the SIU_ECCR are read/write and reset by the asynchronous reset signal.
Offset:
SI 0x0980
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MATCH DISNEX
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
TES
T
LOC
K
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-22. Chip Configuration Register (SIU_CCR)
Table 6-24. SIU_CCR Field Descriptions
Field
Description
bits 0–13
Reserved.
MATCH
Compare Register Match. The MATCH bit is a read-only bit that holds the value of the match input
signal to the SIU. The match input is asserted if the values in the SIU_CMPAH/SIU_CMPAL and
SIU_CMPBH/SIU_CMPBL are equal.
0 Match input signal is negated.
1 Match input signal is asserted.
DISNEX
Disable Nexus. The DISNEX bit is a read-only bit that holds the value of the Nexus disable input
signal to the SIU. When system reset negates, the value in this bit depends on the censorship
control word and the boot configuration bits.
0 Nexus disable input signal negated.
1 Nexus disable input signal asserted.
bits 16–23
Reserved.
TESTLOCK TEST Lock. The TESTLOCK bit prevents access to Freescale internal test features.
These internal test features are enabled by writing to reserved test bits in the device. Setting the
TESTLOCK bit locks the test bits so that they cannot be changed inadvertently by runaway code.
Customer initialization code should always set this bit.
0 Internal test features could be enabled.
1 Internal test features are disabled.
bits 25–31
Reserved.
Note: Reserved bit 30 is writeable, but writing to this bit has no effect other than to update the
value of the register. For future compatibility, this bit should be written to zero. This bit is
reset with POR only.
