System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
6-38
Freescale Semiconductor
Preliminary
6.3.2.26
Halt Register (SIU_HLT)
The SIU_HLT register is used to disable the clocks to various modules. Each bit drives a separate halt
request to the associated peripheral.
shows these connected outputs.
Table 6-26. SIU_SYSCLK Field Descriptions
Field
Description
SYSCLKSEL
System Clock Select. The SYSCLKSEL bit selects the source for the system clock.
00 System clock supplied by 16 MHz IRC
01 System clock supplied by XOSC
10 System clock supplied by PLL
11 Reserved (defaults to 16 MHz IRC)
SYSCLKDIV
System Clock Divide. The SYSCLKDIV bits select the divider value for the system clock. The
SYSCLKDIV divider is required in addition to the RFD to allow the other sources for the system clock
(16 MHz IRC and OSC) to be divided to slowest frequencies to improve power.
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
SWTCLKSEL
Software Watchdog Timer Clock Select. The SWTCLKSEL bit determines whether the software
watchdog timer counter uses 16 MHz IRC or the system clock.
0 System Clock (Note: out of reset, the system clock is driven by the 16 MHz IRC)
1 16 MHz IRC
bits 5–15
Reserved.
LPCLKDIVn
Low-Power Peripheral Clock Divides. The LPCLKDIV bits select the divider values for each peripheral
group.
defines the module groups that are affect by LPCLKDIVn.
00 Divide by 1
01 Divide by 2
10 Divide by 4
11 Divide by 8
Table 6-27. LPCLKDIV Module Groups
LPCLKDIVn
Modules
LPCLKDIV0
FlexCAN_A, DSPI_A
LPCLKDIV1
ESCI_A, I
2
C_A, PIT
LPCLKDIV2
FlexCAN_B-F
LPCLKDIV3
DSPI_B-D
LPCLKDIV4
ESCI_B-H
LPCLKDIV5
eMIOS
LPCLKDIV6
MLB
LPCLKDIV7
Reserved
