System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
6-45
Preliminary
6.3.2.37
Parallel GPIO Pin Data Input Register 4 (SIU_PGPDI4)
Reads to the SIU_PGPDI4 register provide the parallel GPIO pin data input for PJ0:PJ15 and PK0:PK1.
Writes have no effect.
Reads of this register are coherent with the registers SIU_GPDI128_131, SIU_GPDI132_135,
SIU_GPDI136_139, SIU_GPDI140_143, and SIU_GPDI144_145.
6.3.2.38
Masked Parallel GPIO Pin Data Output Registers
The purpose of these registers is to allow any combination of bits in a 16-bit parallel GPIO pin data output
port to be updated in a single 32-bit write operation, while allowing other bits to maintain their previous
state. This is accomplished by grouping each 16-bit port with a 16-bit mask register, and only updating
those bits in the data register for which the corresponding mask bit is set.
For example, if the current state of the port B parallel GPIO pin data output register is 0x1234 and you
want to change only bits [12:15] (i.e., the 4) to be an 8, then a 32-bit write with a mask value of 0x000C
and data value of 0x0008 (i.e. 0x000C_0008) would be performed.
This register always reads as 0.
6.3.2.38.1
Masked Parallel GPIO Pin Data Output Register 1 (SIU_MPGPDO1)
The SIU_MPGPDO1 register contains the Masked Parallel GPIO Pin Data Output for PB[0:15].
Offset:
SI 0x0C4C
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PG0:PG15
W
Reset
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PH0:PH15
W
Reset
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Figure 6-39. Parallel GPIO Pin Data Input Register 3 (SIU_PGPDI3)
Offset:
SI 0x0C50
Access: User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PJ0:PJ15
W
Reset
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PK0:PK1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-40. Parallel GPIO Pin Data Input Register 4 (SIU_PGPDI4)
