MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
9-1
Preliminary
Chapter 9
Interrupt Controller (INTC)
9.1
Introduction
The INTC provides priority-based preemptive scheduling of interrupt service requests (ISRs). This
scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC supports 294
interrupt requests. It is targeted to work with Power Architecture technology and automotive applications
where the ISRs nest to multiple levels, but it also can be used with other processors and applications.
For high-priority interrupt requests in these target applications, the time from the assertion of the
peripheral’s interrupt request to when the processor is performing useful work to service the interrupt
request needs to be minimized. The INTC supports this goal by providing a unique vector for each
interrupt request source. It also provides 16 priorities so that lower priority ISRs do not delay the execution
of higher priority ISRs. Because each individual application will have different priorities for each source
of interrupt request, the priority of each interrupt request is configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests.
These software settable interrupt requests can also be used to separate the work involved in servicing an
interrupt request into a high-priority portion and a low-priority portion. The high-priority portion is
initiated by a peripheral interrupt request, but then the ISR can assert a software settable interrupt request
to finish the servicing in a lower priority ISR. Therefore these software settable interrupt requests can be
used instead of the peripheral ISR scheduling a task through the RTOS.
9.1.1
Features
•
Supports 286 peripheral and eight software-settable interrupt request sources.
•
Each interrupt source can be steered by software to processor 0 (Z1), processor 1 (Z0) or both
processors interrupt request outputs.
NOTE
By default, processor 0 (Z1) receives all interrupt requests, so backward
compatibility with single processor systems is maintained.
When sending an interrupt to both cores, the user must take care to prevent
the interrupt from going away from the other core when not expected.
•
9-bit vector
— Unique vector for each interrupt request source
