Interrupt Controller (INTC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
9-2
Freescale Semiconductor
Preliminary
— Hardware connection to processor or read from register
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Each interrupt source can be programmed to one of 16 priorities
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Preemption
— Preemptive prioritized interrupt requests to processor
— ISR at a higher priority preempts ISRs or tasks at lower priorities
— Automatic pushing or popping of preempted priority to or from a LIFO
— Ability to modify the ISR or task priority; modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
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Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
9.1.2
Block Diagram
is a block diagram of the interrupt controller (INTC).
