Interrupt Controller (INTC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
9-7
Preliminary
9.3.2.2
INTC Current Priority Register for Processor 0 (Z1) (INTC_CPR_PRC0)
The current priority register masks any peripheral or software settable interrupt request at the same or
lower priority of the current value than the PRI field in INTC_CPR_PRC0 from generating an interrupt
request to processor 0 (Z1). When INTC_IACKR_PRC0 is read in software vector mode, or the interrupt
acknowledge signal from the processor is asserted in hardware vector mode, the value of PRI is pushed
onto the LIFO, and PRI is updated with the priority of the preempting interrupt request. When
INTC_SSCIR0_3–INTC_SSCIR4_7 is written, the LIFO is popped into the INTC_CPR_PRC0’s PRI
field. An exception case in hardware vector mode to this behavior is described in
.”
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 9.5.5, “Priority Ceiling Protocol
.”
Table 9-2. INTC_MCR Field Descriptions
Field
Description
VTES_PRC1
VTES_PRC0
For software mode only, the Vector Table Entry Size for Processor 0 (Z1) and Processor 1 (Z0). The
VTES_PRC0 bit controls the number of 0s to the right of INTVEC_PRC0 in INTC_IACKR_PRC0. The
VTES_PRC1 bit controls the number of 0s to the right of INTVEC_PRC1 in INTC_IACKR_PRC1. If the
contents of INTC_IACKR_PRC0 or INTC_IACKR_PRC1 are used as an address of an entry in a vector table,
then the number of rightmost 0s will determine the size of each vector table entry.
0 4 bytes of address offset between vectors.
1 8 bytes of address offset between vectors.
Note: A larger table may be useful if the interrupt service routines (ISR) require very few instructions;
however, more typically, the smaller 4-byte size is used as a jump table to the actual ISRs.
HVEN_PRC1
HVEN_PRC0
Hardware Vector Enable for Processor 0 (Z1) and Processor 1 (Z0). The HVEN bit controls whether the INTC
is in hardware vector mode or software vector mode. Refer to
” for details of
handshaking with the processor in each mode.
0 Software vector mode.
1 Hardware vector mode.
Offset: 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRI
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Figure 9-3. INTC Current Priority Register for Processor 0 (Z1) (INTC_CPR_PRC0)
Table 9-3. INTC_CPR_PRC0 Field Descriptions
Field
Description
PRI
Priority. PRI is the priority of the currently executing ISR according to the field values defined in
.
