Interrupt Controller (INTC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
9-20
Freescale Semiconductor
Preliminary
Figure 9-14. Hardware Vector Mode Handshaking Timing Diagram
9.5
Initialization/Application Information
9.5.1
Initialization Flow
After exiting reset, all of the PRI
n
and PRC_SEL
n
fields in INTC_PSR0_3–INTC_PSR292_293 will be
0, and PRI in both INTC_CPR_PRC0 and INTC_CPR_PRC1 will be 15. These reset values prevent the
INTC from asserting interrupt requests to the processors. Furthermore, the peripherals must have a bit to
enable or mask peripheral interrupt request signals. An initialization sequence for allowing the peripheral
and software settable interrupt requests to cause an interrupt request to the processor is:
interrupt_request_initialization:
configure VTES_PRC0,VTES_PRC1,HVEN_PRC0 and HVEN_PRC1 in INTC_MCR
configure VTBA_PRC
n
in INTC_IACKR_PRC
n
raise the PRI
n
fields and set the PRC_SEL
n
fields to the desired processor in INTC_PSR
n
_
n
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR_PRC
n
to zero
enable processor(s) recognition of interrupts
9.5.2
Interrupt Exception Handler
These example interrupt exception handlers use Power Architecture assembly code.
0
108
0
1
0
Clock
Interrupt request to processor
Hardware vector enable
Interrupt vector
Interrupt acknowledge
Read INTC_IACKR_PRCn
Write INTC_EOIR_PRCn
INTVEC in INTC_IACKR_PRCn
PRI in INTC_CPR_PRCn
Peripheral interrupt request 100
0
108
