Interrupt Controller (INTC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
9-22
Freescale Semiconductor
Preliminary
bl
ISR
n
# branch to ISR for interrupt with vector
x
epilog:
lis
r3,hi(INTC_EOIR_PRC
n
)
# form INTC_EOIR_PRC
n
address
ori
r3,r3,lo(INTC_EOIR_PRC
n
)
li
r4,0x0
# form 0 to write to INTC_EOIR_PRC
n
stw
r4,0x0(r3)
# store to INTC_EOIR_PRC
n
, informing INTC to lower priority
code to restore context required by EABI and disable processor recognition of interrupts
code to restore SRR0 and SRR1
rfi
ISR
n
:
code to service the interrupt event
code to clear flag bit which drives interrupt request to INTC
blr
# branch to epilog
9.5.3
ISR, RTOS, and Task Hierarchy
The RTOS and all of the tasks under its control typically execute with PRI in INTC_CPR_PRC0 or
INTC_CPR_PRC1 having a value of 0. The RTOS executes the tasks according to whatever priority
scheme it may have, but that priority scheme is independent and has a lower priority of execution than the
priority scheme of the INTC. In other words, the ISRs execute above INTC_CPR_PRC
n
priority 0 and
outside the control of the RTOS, the RTOS executes at INTC_CPR_PRC
n
priority 0, and while the tasks
execute at different priorities under the control of the RTOS, they also execute at INTC_CPR_PRC
n
priority 0.
If a task shares a resource with an ISR and the PCP is being used to manage that shared resource, then the
task’s priority can be elevated in the INTC_CPR_PRC
n
while the shared resource is being accessed.
An ISR whose PRI
n
in INTC_PSR0_3–INTC_PSR292_293 has a value of 0 will not cause an interrupt
request to the selected processor, even if its peripheral or software settable interrupt request is asserted. For
a peripheral interrupt request, not setting its enable bit or disabling the mask bit causes it to remain negated,
which consequently does not cause an interrupt request to the processor. Because the ISRs are outside the
control of the RTOS, this ISR will not run unless called by another ISR or the interrupt exception handler,
perhaps after executing another ISR.
9.5.4
Order of Execution
An ISR with a higher priority can preempt an ISR with a lower priority, regardless of the unique vectors
associated with each of their peripheral or software settable interrupt requests. However, if multiple
peripheral or software settable interrupt requests are asserted, more than one has the highest priority, and
that priority is high enough to cause preemption, the INTC selects the one with the lowest unique vector
regardless of the order in time that they asserted. However, the ability to meet deadlines with this
scheduling scheme is no less than if the ISRs execute in the time order that their peripheral or software
settable interrupt requests asserted.
