Interrupt Controller (INTC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
9-26
Freescale Semiconductor
Preliminary
processor has completed accessing the block of data, the first processor again wants to access it. The
accesses to the block of data must be done coherently. To do this, the first processor writes a 1 to a SETn
bit on the second processor. After accessing the block of data, the second processor clears the
corresponding CLRn bit and then writes 1 to a SETn bit on the first processor, informing it that it can now
access the block of data.
9.5.8
Lowering Priority Within an ISR
A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans
multiple priorities (see
Section 9.5.7.1, “Scheduling a Lower Priority Portion of an ISR”)
is to lower the
current priority. However, the INTC has a LIFO whose depth is determined by the number of priorities.
NOTE
Lowering the PRI value in either INTC_CPR_PRC0 or INTC_CPR_PRC1
within an ISR to below the ISR’s corresponding PRI value in
INTC_PSR0_3–INTC_PSR292_293 allows more preemptions than the
LIFO depth can support.
Therefore, the INTC does not support lowering the current priority within an ISR as a way to avoid
preemptive scheduling inefficiencies.
9.5.9
Negating an Interrupt Request Outside of its ISR
9.5.9.1
Negating an Interrupt Request as a Side Effect of an ISR
Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits and their corresponding interrupt
requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of
other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is
executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.
9.5.9.2
Negating Multiple Interrupt Requests in One ISR
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because
it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed.
9.5.9.3
Proper Setting of Interrupt Request Priority
Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the
intentional clearing a flag bit, the priorities of the peripheral or software settable interrupt requests for these
other flag bits must be selected properly. Their PRI
n
values in INTC_PSR0_3–INTC_PSR292_293 must
be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those flag
bits can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other flag
bits also has the same timing relationship to the writing to INTC_SSCIR0_3–INTC_SSCIR4_7 as the
clearing of the flag bit that caused the present ISR to be executed (see
Section 9.4.3.1.2, “End of Interrupt
”)
.
